Lin Shen and Rado Tibor. Computer studies of Turing machine problems. Journal of the Association for Computing Machinery, vol. 12 , pp. 196–212.Brady Allen H.. The conjectured highest scoring machines for Rado's Σ for the value k = 4. IEEE transactions on electronic computers, vol. EC-15 , pp. 802–803.Green Milton W.. A lower bound on Rado's sigma function for binary Turing machines. Switching circuit theory and logical design, Proceedings of the Fifth Annual Symposium, Princeton University, Princeton, N.J., November 11-13, 1964, The Institute of Electrical and Electronics Engineers, Inc., New York 1964, pp. 91–94 [Book Review]

Journal of Symbolic Logic 40 (4):617-617 (1975)
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Review: Shen Lin, Tibor Rado, Computer Studies of Turing Machine Problems; Allen H. Brady, The Conjectured Highest Scoring Machines for Rado's $sum(k)$ for the Value $K = 4$; Milton W. Green, A Lower Bound on Rado's Sigma Function for Binary Turing Machines. [REVIEW]H. B. Enderton - 1975 - Journal of Symbolic Logic 40 (4):617-617.
J. Hartmanis and R. E. Stearns. Computational complexity of recursive sequences. Switching circuit theory and logical design, Proceedings of the Fifth Annual Symposium, Princeton University, Princeton, N.J., November 11–13, 1964, The Institute of Electrical and Electronics Engineers, Inc., New York1964, pp. 82–90. [REVIEW]Jiří Bečvář - 1967 - Journal of Symbolic Logic 32 (1):121-122.
H. Allen Curtis. A functional canonical form. Journal of the Association for Computing Machinery, vol. 6 , pp. 245–258. - H. Allen Curtis. Multifunctional circuits in functional canonical form. Journal of the Association for Computing Machinery, vol. 6 , pp. 538–547. - H. Allen Curtis. A new approach to the design of switching circuits. D. Van Nostrand Company, Inc., Princeton-Toronto-London-New York, 1962, viii + 635 pp. - R. L. Ashenhurst. The decomposition of switching functions. Therein, pp. 571–602. - Theodore Singer. The decomposition chart as a theoretical aid. Therein, pp. 602–620. [REVIEW]Harold S. Stone - 1972 - Journal of Symbolic Logic 37 (4):760-762.
Stearns R. E., Hartmanis J., and Lewis P. M. II. Hierarchies of memory limited computations. Sixth Annual Symposium on Switching Circuit Theory and Logical Design, University of Michigan, Ann Arbor, Mich., The Institute of Electrical and Electronics Engineers, Inc., New York 1965, pp. 179–190. [REVIEW]Walter J. Savitch - 1972 - Journal of Symbolic Logic 37 (3):624-625.
R. H. Urbano and R. K. Mueller. A topological method for the determination of the minimal forms of a Boolean function. Transactions of the IRE Professional. Group on Electronic Computers, vol. EC-5 no. 3 , pp. 126–132. - David M. Brender. The logical procedures needed for finding the minimals of a Boolean function on a digital computer. Summaries of talks presented at the Summer Institute for Symbolic Logic, Cornell University, 1957, 2nd edn., Communications Research Division, Institute for Defense Analyses, Princeton, N.J., 1960, p. 210. [REVIEW]Thomas H. Mott - 1960 - Journal of Symbolic Logic 25 (4):370-373.
R. H. Urbano and R. K. Mueller. A topological method for the determination of the minimal forms of a Boolean function. Transactions of the IRE Professional. Group on Electronic Computers, vol. EC-5 no. 3 , pp. 126–132. - David M. Brender. The logical procedures needed for finding the minimals of a Boolean function on a digital computer. Summaries of talks presented at the Summer Institute for Symbolic Logic, Cornell University, 1957, 2nd edn., Communications Research Division, Institute for Defense Analyses, Princeton, N.J., 1960, p. 210. [REVIEW]Thomas H. Mott - 1960 - Journal of Symbolic Logic 25 (4):368-370.
McCluskey E. J. Jr., Minimal sums for Boolean functions having many unspecified fundamental products. Switching circuit theory and logical design, Proceedings of the Second Annual Symposium, Detroit, Mich., October 17–20,1961, and papers from the First Annual Symposium, Chicago, III., October 9–14,1960, American Institute of Electrical Engineers, New York 1961, pp. 10–17; also Transactions of the American Institute of Electrical Engineers, vol. 81 part 1 , pp. 387–392. [REVIEW]Thomas H. Mott - 1967 - Journal of Symbolic Logic 32 (2):263-264.
Meo. Angelo Raffaele On the minimal third order expression of a Boolean function. Proceedings of the Third Annual Symposium on Switching Circuit Theory and Logical Design, Chicago, October 7–12, 1962, American Institute of Electrical Engineers, New York 1962, pp. 5–24. [REVIEW]A. K. Choudhury - 1968 - Journal of Symbolic Logic 32 (4):540-540.
Arden Dean N.. Delayed-logic and finite-state machines. Switching circuit theory and logical design, Proceedings of the Second Annual Symposium, Detroit, Mich., October 17–20, 1961, and papers from the First Annual Symposium, Chicago, III., October 9–14,1960, American Institute of Electrical Engineers, New York 1961, pp. 133–151. [REVIEW]Robert McNaughton - 1971 - Journal of Symbolic Logic 36 (1):151-151.
Patrick C. Fischer. On formalisms for Turing machines. Journal of the Association for Computing Machinery, vol. 12 , pp. 570–580. - Stål Aanderaa and Patrick C. Fischer. The solvability of the halting problem for 2-state Post machines. Journal of the Association for Computing Machinery, vol. 14 , pp. 677–682. - Patrick C. Fischer. Quantificational variants on the halting problem for Turing machines. Zeitschrift für mathematische Logik und Grundlagen der Mathematik, vol. 15 , pp. 211–218. [REVIEW]Gabor T. Herman - 1971 - Journal of Symbolic Logic 36 (3):532-534.

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